Over the last several decades, significant advancements have been made in personal computer (PC) microprocessor architecture and fabrication techniques, to improve performance and control costs. With each successive generation, an increasing number of functions have been integrated into a processor integrated circuit die. This has been enabled by shrinking the size of the constituent transistor elements. Performance improvements have been obtained by for example increasing the processor dock frequency. As a result, each successive generation of such processors is more powerful and has increasing overall power consumption.
The power consumption of a processor is proportional to a product of its power supply voltage and current. As processors become more advanced, they demand a lower power supply voltage but higher power supply current. For example, in the early days of microprocessors offered by Intel Corp. of Santa Clara, Calif., transistor count per die was in the low 100,000s, processor clocks were running at around 100 MHz, supply voltages were at 5V DC, and supply current was no more than 10 A (depending on the activity level of the processor). With more recent PENTIUM dass processors, transistor count per die is well above 1 million, clocks are in the GHz range, the power supply voltage needs to be dropped to about 1.2V DC or less, while current draw (at high activity levels) easily surpasses 100 A.
The supply voltage needs to be regulated to stay within a certain range, in the presence of operating temperature variations and as the processor transitions between different activity levels. However, the smaller supply voltages have resulted in tighter ranges being required, in the face of large current swings. This has led to many challenges in providing low cost power delivery for advanced processors. Poorly designed power delivery networks can be unstable or have large oscillatory behavior due to too little damping, and such power delivery networks are excluded from further discussion here.
To ensure reliable power delivery for its microprocessor families, Intel has set voltage regulator design guidelines. A voltage regulator (VR) is an electronic circuit that draws current from a power source, to feed the processor and maintain a well-regulated power supply voltage for the processor. The VR maintains a setpoint voltage (e.g., at a so-called “Vcc” node of the processor), using a feedback control loop that repeatedly senses deviations from the setpoint, and corrects for them by increasing or decreasing the amount of current drawn from the source. For greater power conversion efficiency, switching-type regulators are used that draw current from the source using transistor or similar devices that turn on and off at high rates and stay on for relatively short pulses. The setpoint voltage is maintained by suitably controlling the pulse widths.
A VR can be made to respond quickly to deviations from the setpoint voltage (both voltage droops and voltage spikes). However, with present generation processors and VR technology, the supply voltage is not likely to stay within its set tolerance band unless substantial power supply filtering or capacitive decoupling is added. The addition of more filtering helps reduce the voltage and current ripple that is present at the output of every switching regulator. In operation, present generation processors exhibit very fast supply current changes (referred to as deltaI/deltat current surges or steps) that are in the range of 50 A/nsec at the processor, which cause voltage droops on the supply node. Capacitive decoupling refers to the addition of structures (e.g., on-die or in package with the processor) that act as fast energy storage devices, to supply the processor with the needed deltaI, and thereby reduce droop on the power supply node.
An approach for cost effective power delivery is to specify a linear DC loadline or voltage-current relationship for the processor, where the VR is to vary the power supply voltage (Vcc) as a function of processor current (Icc), from zero current to maximum current. The slope of the DC loadline is known as the DC loadline resistance. See plot 102 for Vcc vs. Icc in FIG. 1. This is also referred to as adaptive voltage positioning (AVP). This is in contrast to positioning a nominal voltage midway between Vmin and Vmax, and maintaining a current-independent voltage level, leaving only half of the voltage window for either the transient voltage droop or spike.
AVP keeps Vcc high (e.g., slightly below Vmax) when Icc is low, anticipating a voltage droop when current ramps up, thereby leaving the entire voltage window for the droop. Similarly, AVP keeps the voltage low (e.g., slightly above Vmin) at maximum Icc, anticipating a subsequent voltage spike. FIG. 1 also shows a tolerance band, around a nominal loadline 107 that has a constant slope 109. Ideally, using AVP effectively halves the voltage noise amplitude compared to VRs without AVP. In actual practice, the benefit is generally less than the ideal, but still generally quite significant. The reduction in effective noise amplitude helps reduce the cost of power delivery, by relaxing some of the capacitive decoupling and/or power supply filtering requirements.